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<div class="header">
  <div class="summary">
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle">
<div class="title">Functions<div class="ingroups"><a class="el" href="group__group__sysclk.html">SysClk       (System Clock)</a> &raquo; <a class="el" href="group__group__sysclk__fll.html">Frequency Locked Loop (FLL)</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gad9d9c36d022475746375bddaba2b2065"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__fll__funcs.html#gad9d9c36d022475746375bddaba2b2065">Cy_SysClk_FllConfigure</a> (uint32_t inputFreq, uint32_t outputFreq, <a class="el" href="group__group__sysclk__fll__enums.html#ga777e08424e26c9cd8c2602b2114e716b">cy_en_fll_pll_output_mode_t</a> outputMode)</td></tr>
<tr class="memdesc:gad9d9c36d022475746375bddaba2b2065"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the FLL, for best accuracy optimization.  <a href="#gad9d9c36d022475746375bddaba2b2065">More...</a><br /></td></tr>
<tr class="separator:gad9d9c36d022475746375bddaba2b2065"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e2e272b670cc52ab984291afae6a1fa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__fll__funcs.html#ga0e2e272b670cc52ab984291afae6a1fa">Cy_SysClk_FllManualConfigure</a> (const <a class="el" href="structcy__stc__fll__manual__config__t.html">cy_stc_fll_manual_config_t</a> *config)</td></tr>
<tr class="memdesc:ga0e2e272b670cc52ab984291afae6a1fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Manually configures the FLL based on user inputs.  <a href="#ga0e2e272b670cc52ab984291afae6a1fa">More...</a><br /></td></tr>
<tr class="separator:ga0e2e272b670cc52ab984291afae6a1fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e8ceae09a6a3e825c3ab9cea5561eed"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__fll__funcs.html#ga8e8ceae09a6a3e825c3ab9cea5561eed">Cy_SysClk_FllGetConfiguration</a> (<a class="el" href="structcy__stc__fll__manual__config__t.html">cy_stc_fll_manual_config_t</a> *config)</td></tr>
<tr class="memdesc:ga8e8ceae09a6a3e825c3ab9cea5561eed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reports the FLL configuration settings.  <a href="#ga8e8ceae09a6a3e825c3ab9cea5561eed">More...</a><br /></td></tr>
<tr class="separator:ga8e8ceae09a6a3e825c3ab9cea5561eed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a008909d3f50d85fb8d8c9f56ed8886"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a> (uint32_t timeoutus)</td></tr>
<tr class="memdesc:ga5a008909d3f50d85fb8d8c9f56ed8886"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the FLL.  <a href="#ga5a008909d3f50d85fb8d8c9f56ed8886">More...</a><br /></td></tr>
<tr class="separator:ga5a008909d3f50d85fb8d8c9f56ed8886"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab266867b8e4f71d58467c33c53f6f0e2"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__fll__funcs.html#gab266867b8e4f71d58467c33c53f6f0e2">Cy_SysClk_FllIsEnabled</a> (void)</td></tr>
<tr class="memdesc:gab266867b8e4f71d58467c33c53f6f0e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reports whether or not the FLL is enabled.  <a href="#gab266867b8e4f71d58467c33c53f6f0e2">More...</a><br /></td></tr>
<tr class="separator:gab266867b8e4f71d58467c33c53f6f0e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3227d4ab9e531127a7cc7bd27c49a499"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__fll__funcs.html#ga3227d4ab9e531127a7cc7bd27c49a499">Cy_SysClk_FllLocked</a> (void)</td></tr>
<tr class="memdesc:ga3227d4ab9e531127a7cc7bd27c49a499"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reports whether the FLL is locked first time during FLL starting.  <a href="#ga3227d4ab9e531127a7cc7bd27c49a499">More...</a><br /></td></tr>
<tr class="separator:ga3227d4ab9e531127a7cc7bd27c49a499"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3517689f7b87299fecbaf6eea8656146"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__fll__funcs.html#ga3517689f7b87299fecbaf6eea8656146">Cy_SysClk_FllDisable</a> (void)</td></tr>
<tr class="memdesc:ga3517689f7b87299fecbaf6eea8656146"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the FLL and the CCO.  <a href="#ga3517689f7b87299fecbaf6eea8656146">More...</a><br /></td></tr>
<tr class="separator:ga3517689f7b87299fecbaf6eea8656146"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga53e22520cb9e7ee2b103d43513343803"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__fll__funcs.html#ga53e22520cb9e7ee2b103d43513343803">Cy_SysClk_FllOutputDividerEnable</a> (bool enable)</td></tr>
<tr class="memdesc:ga53e22520cb9e7ee2b103d43513343803"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables/Disables the FLL output divider.  <a href="#ga53e22520cb9e7ee2b103d43513343803">More...</a><br /></td></tr>
<tr class="separator:ga53e22520cb9e7ee2b103d43513343803"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e45b36747a2be6610f6fc9daefae02b"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__fll__funcs.html#ga0e45b36747a2be6610f6fc9daefae02b">Cy_SysClk_FllGetFrequency</a> (void)</td></tr>
<tr class="memdesc:ga0e45b36747a2be6610f6fc9daefae02b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the output frequency of the FLL.  <a href="#ga0e45b36747a2be6610f6fc9daefae02b">More...</a><br /></td></tr>
<tr class="separator:ga0e45b36747a2be6610f6fc9daefae02b"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Function Documentation</h2>
<a id="gad9d9c36d022475746375bddaba2b2065"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad9d9c36d022475746375bddaba2b2065">&#9670;&nbsp;</a></span>Cy_SysClk_FllConfigure()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a> Cy_SysClk_FllConfigure </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>inputFreq</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>outputFreq</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__sysclk__fll__enums.html#ga777e08424e26c9cd8c2602b2114e716b">cy_en_fll_pll_output_mode_t</a>&#160;</td>
          <td class="paramname"><em>outputMode</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Configures the FLL, for best accuracy optimization. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">inputFreq</td><td>frequency of input source, in Hz</td></tr>
    <tr><td class="paramname">outputFreq</td><td>Desired FLL output frequency, in Hz. Allowable range is 24 MHz to 100 MHz. In all cases, FLL_OUTPUT_DIV must be set; the output divide by 2 option is required.</td></tr>
    <tr><td class="paramname">outputMode</td><td><a class="el" href="group__group__sysclk__fll__enums.html#ga777e08424e26c9cd8c2602b2114e716b">cy_en_fll_pll_output_mode_t</a> If output mode is bypass, then the output frequency equals the input source frequency regardless of the frequency parameter values.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Error / status code: <br />
CY_SYSCLK_SUCCESS - FLL successfully configured <br />
CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled <br />
CY_SYSCLK_BAD_PARAM - desired output frequency is out of valid range <br />
CY_SYSCLK_UNSUPPORTED_STATE - FLL is not present</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Call this function after changing the FLL input frequency, for example if <a class="el" href="group__group__sysclk__path__src__funcs.html#ga517f603266062d0013947ea950ed5b60">Cy_SysClk_ClkPathSetSource()</a> is called.</dd>
<dd>
Do not call this function when the FLL is enabled. If it is called, then this function returns with an CY_SYSCLK_INVALID_STATE return value and no register updates.</dd>
<dd>
Call <a class="el" href="group__group__startup__config__system__functions.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> after this function calling if it affects the CLK_HF0 frequency.</dd>
<dd>
Call <a class="el" href="group__group__syslib__functions.html#ga8b897f8554957f9393f645d5ab1106c9">Cy_SysLib_SetWaitStates</a> before calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is increasing.</dd>
<dd>
Call <a class="el" href="group__group__syslib__functions.html#ga8b897f8554957f9393f645d5ab1106c9">Cy_SysLib_SetWaitStates</a> after calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is decreasing.</dd>
<dd>
On PSoC 64 devices the configuration on the PRA driver will be reflected after <a class="el" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a> call. Any call to <a class="el" href="group__group__sysclk__fll__funcs.html#ga8e8ceae09a6a3e825c3ab9cea5561eed">Cy_SysClk_FllGetConfiguration</a> before calling <a class="el" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a> returns old configuration values.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    <span class="comment">/* Scenario: FLL needs to source HFCLK0, which must operate at 100 MHz.</span></div><div class="line"><span class="comment">                 The IMO sources the FLL at 8MHz. Startup time is not an issue</span></div><div class="line"><span class="comment">                 and manual configuration of the FLL is not needed. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Set the FLL source (path 0 mux) to be the IMO */</span></div><div class="line">    (void)<a class="code" href="group__group__sysclk__path__src__funcs.html#ga517f603266062d0013947ea950ed5b60">Cy_SysClk_ClkPathSetSource</a>(0UL, <a class="code" href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6a01c7cbab413a99daa41d2fb7a0340955">CY_SYSCLK_CLKPATH_IN_IMO</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Auto-configure the FLL */</span></div><div class="line">    <span class="keywordflow">if</span> (<a class="code" href="group__group__sysclk__returns.html#ggad6699a184e2e3c01433251b0981558f3a1563f761f963757b339ff05eb5a690ec">CY_SYSCLK_SUCCESS</a> != <a class="code" href="group__group__sysclk__fll__funcs.html#gad9d9c36d022475746375bddaba2b2065">Cy_SysClk_FllConfigure</a>(<a class="code" href="group__group__sysclk__macros.html#ga9b98d83b0a60b378966d56f7636d85a6">CY_SYSCLK_IMO_FREQ</a>,               <span class="comment">/* Input clock = 8 MHz */</span></div><div class="line">                                                    100000000UL,                      <span class="comment">/* Output clock = 100 MHz */</span></div><div class="line">                                                    <a class="code" href="group__group__sysclk__fll__enums.html#gga777e08424e26c9cd8c2602b2114e716baf9198d7cbbee5db8e8c48375125aee74">CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT</a>))  <span class="comment">/* Bypass Mux to FLL Output */</span></div><div class="line">    {</div><div class="line">        <span class="comment">/* Insert error handling */</span></div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* Enable the FLL with 2000 microsecond timeout */</span></div><div class="line">    <span class="keywordflow">if</span> (<a class="code" href="group__group__sysclk__returns.html#ggad6699a184e2e3c01433251b0981558f3a1563f761f963757b339ff05eb5a690ec">CY_SYSCLK_SUCCESS</a> != <a class="code" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a>(2000UL))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Insert error handling */</span></div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* Set the HFCLK0 source to clock path 0 */</span></div><div class="line">    (void)<a class="code" href="group__group__sysclk__clk__hf__funcs.html#ga2d39c7e5111f9ba0738f032a98b4593e">Cy_SysClk_ClkHfSetSource</a>(0UL, <a class="code" href="group__group__sysclk__clk__hf__enums.html#ggabac2d6b9124a00860dcd781a922788d6ab67e691f04cd3aecb2a4cbf8bbd5b787">CY_SYSCLK_CLKHF_IN_CLKPATH0</a>);</div></div><!-- fragment --></dd></dl>

</div>
</div>
<a id="ga0e2e272b670cc52ab984291afae6a1fa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0e2e272b670cc52ab984291afae6a1fa">&#9670;&nbsp;</a></span>Cy_SysClk_FllManualConfigure()</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname"><a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a> Cy_SysClk_FllManualConfigure </td>
          <td>(</td>
          <td class="paramtype">const <a class="el" href="structcy__stc__fll__manual__config__t.html">cy_stc_fll_manual_config_t</a> *&#160;</td>
          <td class="paramname"><em>config</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Manually configures the FLL based on user inputs. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">config</td><td><a class="el" href="structcy__stc__fll__manual__config__t.html">cy_stc_fll_manual_config_t</a></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Error / status code: <br />
CY_SYSCLK_SUCCESS - FLL successfully configured <br />
CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when function returns the PRA error status code <a class="el" href="group__group__pra__enums.html#ga60be13e12e82986f8c0d6c6a6d4f12c5">cy_en_pra_status_t</a> instead of <a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a>. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to <a class="el" href="group__group__pra__enums.html#ga60be13e12e82986f8c0d6c6a6d4f12c5">cy_en_pra_status_t</a> for more details.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Call this function after changing the FLL input frequency, for example if <a class="el" href="group__group__sysclk__path__src__funcs.html#ga517f603266062d0013947ea950ed5b60">Cy_SysClk_ClkPathSetSource()</a> is called.</dd>
<dd>
Do not call this function when the FLL is enabled. If it is called, then this function returns immediately with an CY_SYSCLK_INVALID_STATE return value and no register updates.</dd>
<dd>
Call <a class="el" href="group__group__startup__config__system__functions.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> after this function calling if it affects the CLK_HF0 frequency.</dd>
<dd>
Call <a class="el" href="group__group__syslib__functions.html#ga8b897f8554957f9393f645d5ab1106c9">Cy_SysLib_SetWaitStates</a> before calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is increasing.</dd>
<dd>
Call <a class="el" href="group__group__syslib__functions.html#ga8b897f8554957f9393f645d5ab1106c9">Cy_SysLib_SetWaitStates</a> after calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is decreasing.</dd>
<dd>
On PSoC 64 devices the configuration on the PRA driver will be reflected after <a class="el" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a> call. Any call to <a class="el" href="group__group__sysclk__fll__funcs.html#ga8e8ceae09a6a3e825c3ab9cea5561eed">Cy_SysClk_FllGetConfiguration</a> before calling <a class="el" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a> returns old configuration values.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    <span class="comment">/* Scenario: FLL needs to source HFCLK0, which must operate at 100 MHz.</span></div><div class="line"><span class="comment">                 The IMO sources the FLL at 8MHz. The characteristics of the</span></div><div class="line"><span class="comment">                 FLL lock parameters are already known and the startup time</span></div><div class="line"><span class="comment">                 for the FLL configuration must be minimized. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Refer to the TRM for the full set of equations used to calculate the parameters */</span></div><div class="line">    <span class="keyword">const</span> <a class="code" href="structcy__stc__fll__manual__config__t.html">cy_stc_fll_manual_config_t</a> fllConfig =</div><div class="line">    {</div><div class="line">        <span class="comment">/*.fllMult =*/</span>         1725UL,                        <span class="comment">/* Multiplier for CCO frequency */</span></div><div class="line">        <span class="comment">/*.refDiv =*/</span>          (uint16_t)69u,                 <span class="comment">/* Reference clock divider */</span></div><div class="line">        <span class="comment">/*.ccoRange =*/</span>        <a class="code" href="group__group__sysclk__fll__enums.html#ggac8760ee841ca24255c9a4fee494b79aaa6c50c6395080bcf0cc45094a6eaf22b4">CY_SYSCLK_FLL_CCO_RANGE4</a>,      <span class="comment">/* Target CCO range of 200 (100*2) MHz */</span></div><div class="line">        <span class="comment">/*.enableOutputDiv =*/</span> <span class="keyword">true</span>,                          <span class="comment">/* Output divider enabled (divide by 2) */</span></div><div class="line">        <span class="comment">/*.lockTolerance =*/</span>   33u,                           <span class="comment">/* Lock tolerance */</span></div><div class="line">        <span class="comment">/*.igain =*/</span>           7u,                            <span class="comment">/* FLL loop filter integral gain */</span></div><div class="line">        <span class="comment">/*.pgain =*/</span>           5u,                            <span class="comment">/* FLL loop filter proportional gain */</span></div><div class="line">        <span class="comment">/*.settlingCount =*/</span>   8u,                            <span class="comment">/* Wait count before loop measurement restarts */</span></div><div class="line">        <span class="comment">/*.outputMode =*/</span>      <a class="code" href="group__group__sysclk__fll__enums.html#gga777e08424e26c9cd8c2602b2114e716baf9198d7cbbee5db8e8c48375125aee74">CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT</a>,<span class="comment">/* Bypass Mux to FLL Output */</span></div><div class="line">        <span class="comment">/*.cco_Freq =*/</span>        355u                           <span class="comment">/* CCO frequency code (HW controlled during lock) */</span></div><div class="line">    };</div><div class="line"></div><div class="line">    <span class="comment">/* Set the FLL source (path 0 mux) to be the IMO */</span></div><div class="line">    (void)<a class="code" href="group__group__sysclk__path__src__funcs.html#ga517f603266062d0013947ea950ed5b60">Cy_SysClk_ClkPathSetSource</a>(0UL, <a class="code" href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6a01c7cbab413a99daa41d2fb7a0340955">CY_SYSCLK_CLKPATH_IN_IMO</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Configure the FLL lock using pre-calculated values */</span></div><div class="line">    <span class="keywordflow">if</span> (<a class="code" href="group__group__sysclk__returns.html#ggad6699a184e2e3c01433251b0981558f3a1563f761f963757b339ff05eb5a690ec">CY_SYSCLK_SUCCESS</a> != <a class="code" href="group__group__sysclk__fll__funcs.html#ga0e2e272b670cc52ab984291afae6a1fa">Cy_SysClk_FllManualConfigure</a>(&amp;fllConfig))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Insert error handling */</span></div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* Enable the FLL with 2000 microsecond timeout */</span></div><div class="line">    <span class="keywordflow">if</span> (<a class="code" href="group__group__sysclk__returns.html#ggad6699a184e2e3c01433251b0981558f3a1563f761f963757b339ff05eb5a690ec">CY_SYSCLK_SUCCESS</a> != <a class="code" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a>(2000UL))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Insert error handling */</span></div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* Set the HFCLK0 source to clock path 0 */</span></div><div class="line">    (void)<a class="code" href="group__group__sysclk__clk__hf__funcs.html#ga2d39c7e5111f9ba0738f032a98b4593e">Cy_SysClk_ClkHfSetSource</a>(0UL, <a class="code" href="group__group__sysclk__clk__hf__enums.html#ggabac2d6b9124a00860dcd781a922788d6ab67e691f04cd3aecb2a4cbf8bbd5b787">CY_SYSCLK_CLKHF_IN_CLKPATH0</a>);</div></div><!-- fragment --></dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga8e8ceae09a6a3e825c3ab9cea5561eed">&#9670;&nbsp;</a></span>Cy_SysClk_FllGetConfiguration()</h2>

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          <td class="memname">void Cy_SysClk_FllGetConfiguration </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="structcy__stc__fll__manual__config__t.html">cy_stc_fll_manual_config_t</a> *&#160;</td>
          <td class="paramname"><em>config</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reports the FLL configuration settings. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">config</td><td><a class="el" href="structcy__stc__fll__manual__config__t.html">cy_stc_fll_manual_config_t</a></td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>On PSoC 64 devices the configuration on the PRA driver will be reflected after <a class="el" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a> call. Any call to <a class="el" href="group__group__sysclk__fll__funcs.html#ga8e8ceae09a6a3e825c3ab9cea5561eed">Cy_SysClk_FllGetConfiguration</a> before calling <a class="el" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a> returns old configuration values.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    <span class="comment">/* Scenario: The calculated FLL parameters need to be checked. */</span></div><div class="line"></div><div class="line">    <a class="code" href="structcy__stc__fll__manual__config__t.html">cy_stc_fll_manual_config_t</a> fllConfig;</div><div class="line"></div><div class="line">    <span class="comment">/* Auto-configure the FLL */</span></div><div class="line">    <span class="keywordflow">if</span> (<a class="code" href="group__group__sysclk__returns.html#ggad6699a184e2e3c01433251b0981558f3a1563f761f963757b339ff05eb5a690ec">CY_SYSCLK_SUCCESS</a> != <a class="code" href="group__group__sysclk__fll__funcs.html#gad9d9c36d022475746375bddaba2b2065">Cy_SysClk_FllConfigure</a>(8000000UL,                        <span class="comment">/* Input clock = 8 MHz */</span></div><div class="line">                                                    100000000UL,                      <span class="comment">/* Output clock = 100 MHz */</span></div><div class="line">                                                    <a class="code" href="group__group__sysclk__fll__enums.html#gga777e08424e26c9cd8c2602b2114e716baf9198d7cbbee5db8e8c48375125aee74">CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT</a>))  <span class="comment">/* Bypass Mux to FLL Output */</span></div><div class="line">    {</div><div class="line">        <span class="comment">/* Insert error handling */</span></div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* Retrieve the calculated parameters */</span></div><div class="line">    <a class="code" href="group__group__sysclk__fll__funcs.html#ga8e8ceae09a6a3e825c3ab9cea5561eed">Cy_SysClk_FllGetConfiguration</a>(&amp;fllConfig);</div></div><!-- fragment --></dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5a008909d3f50d85fb8d8c9f56ed8886">&#9670;&nbsp;</a></span>Cy_SysClk_FllEnable()</h2>

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          <td class="memname"><a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a> Cy_SysClk_FllEnable </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>timeoutus</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enables the FLL. </p>
<p>The FLL should be configured before calling this function.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">timeoutus</td><td>Amount of time in micro seconds to wait for FLL to lock. If lock doesn't occur, the FLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using <a class="el" href="group__group__sysclk__fll__funcs.html#ga3227d4ab9e531127a7cc7bd27c49a499">Cy_SysClk_FllLocked</a>.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Error / status code: <br />
CY_SYSCLK_SUCCESS - FLL successfully enabled <br />
CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when function returns the PRA error status code <a class="el" href="group__group__pra__enums.html#ga60be13e12e82986f8c0d6c6a6d4f12c5">cy_en_pra_status_t</a> instead of <a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a>. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to <a class="el" href="group__group__pra__enums.html#ga60be13e12e82986f8c0d6c6a6d4f12c5">cy_en_pra_status_t</a> for more details.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>While waiting for the FLL to lock, the FLL bypass mode is set to <a class="el" href="group__group__sysclk__fll__enums.html#gga777e08424e26c9cd8c2602b2114e716baf2893197c53d0101be01ef926a33528b">CY_SYSCLK_FLLPLL_OUTPUT_INPUT</a>. After the FLL is locked, the FLL bypass mdoe is then set to <a class="el" href="group__group__sysclk__fll__enums.html#gga777e08424e26c9cd8c2602b2114e716baf9198d7cbbee5db8e8c48375125aee74">CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT</a>.</dd>
<dd>
Call <a class="el" href="group__group__startup__config__system__functions.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> after calling this function if it affects the CLK_HF0 frequency.</dd>
<dd>
Call <a class="el" href="group__group__syslib__functions.html#ga8b897f8554957f9393f645d5ab1106c9">Cy_SysLib_SetWaitStates</a> before calling this function if the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.</dd>
<dd>
Take into account the possible platform specific clkHf (and further clocking chain links) frequency limitations while using this API.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    <span class="comment">/* Scenario: FLL is configured and needs to be enabled within 2 ms */</span></div><div class="line"></div><div class="line"><span class="preprocessor">    #define CLKPATH0 (0UL)</span></div><div class="line"></div><div class="line">    uint32_t clkPathFreq = 0UL; <span class="comment">/* Variable to store the Clock Path output frequency */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Enable the FLL with a timeout of 2000 microseconds */</span></div><div class="line">    <span class="keywordflow">if</span> (<a class="code" href="group__group__sysclk__returns.html#ggad6699a184e2e3c01433251b0981558f3a1563f761f963757b339ff05eb5a690ec">CY_SYSCLK_SUCCESS</a> == <a class="code" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a>(2000UL))</div><div class="line">    {</div><div class="line">        clkPathFreq = <a class="code" href="group__group__sysclk__path__src__funcs.html#ga54c618c89782d227fb8f292d1dc15625">Cy_SysClk_ClkPathGetFrequency</a>(CLKPATH0);</div><div class="line">        <span class="comment">/* Now clkPathFreq contains an actual FLL frequency */</span></div><div class="line">    }</div><div class="line">    <span class="keywordflow">else</span></div><div class="line">    {</div><div class="line">        <span class="comment">/* Insert error handling */</span></div><div class="line">    }</div></div><!-- fragment --></dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gab266867b8e4f71d58467c33c53f6f0e2">&#9670;&nbsp;</a></span>Cy_SysClk_FllIsEnabled()</h2>

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          <td class="memname">bool Cy_SysClk_FllIsEnabled </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reports whether or not the FLL is enabled. </p>
<dl class="section return"><dt>Returns</dt><dd>false = disabled <br />
true = enabled</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    <span class="comment">/* Scenario: FLL failed to enable and must be reconfigured. Or the FLL is no</span></div><div class="line"><span class="comment">                 longer used and hence needs to be disabled. */</span></div><div class="line"></div><div class="line">    <span class="keywordflow">if</span> (<a class="code" href="group__group__sysclk__fll__funcs.html#gab266867b8e4f71d58467c33c53f6f0e2">Cy_SysClk_FllIsEnabled</a>())</div><div class="line">    {</div><div class="line">        <span class="keywordflow">if</span> (<a class="code" href="group__group__sysclk__returns.html#ggad6699a184e2e3c01433251b0981558f3a1563f761f963757b339ff05eb5a690ec">CY_SYSCLK_SUCCESS</a> != <a class="code" href="group__group__sysclk__fll__funcs.html#ga3517689f7b87299fecbaf6eea8656146">Cy_SysClk_FllDisable</a>())</div><div class="line">        {</div><div class="line">            <span class="comment">/* Insert error handling */</span></div><div class="line">        }</div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* The clocks that relied on the FLL will now run off of the clock that</span></div><div class="line"><span class="comment">       was used to source the FLL (e.g. IMO or ECO). */</span></div></div><!-- fragment --></dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga3227d4ab9e531127a7cc7bd27c49a499">&#9670;&nbsp;</a></span>Cy_SysClk_FllLocked()</h2>

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          <td class="memname">bool Cy_SysClk_FllLocked </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reports whether the FLL is locked first time during FLL starting. </p>
<p>Intended to be used with <a class="el" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a> with zero timeout.</p>
<dl class="section return"><dt>Returns</dt><dd>false = not locked <br />
true = locked</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The unlock occurrence may appear during FLL normal operation, so this function is not recommended to check the FLL normal operation stability.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    <span class="comment">/* Scenario: FLL is configured and needs to be enabled in a non-blocking way */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Enable the FLL without timeout */</span></div><div class="line">    (void)<a class="code" href="group__group__sysclk__fll__funcs.html#ga5a008909d3f50d85fb8d8c9f56ed8886">Cy_SysClk_FllEnable</a>(0UL);</div><div class="line"></div><div class="line">    <span class="comment">/* Check the status of the lock */</span></div><div class="line">    <span class="keywordflow">while</span>(!<a class="code" href="group__group__sysclk__fll__funcs.html#ga3227d4ab9e531127a7cc7bd27c49a499">Cy_SysClk_FllLocked</a>())</div><div class="line">    {</div><div class="line">        <span class="comment">/* Perform other actions while the FLL is locking */</span></div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* FLL Locked. Proceed with further configuration */</span></div></div><!-- fragment --></dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga3517689f7b87299fecbaf6eea8656146">&#9670;&nbsp;</a></span>Cy_SysClk_FllDisable()</h2>

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          <td class="memname"><a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a> Cy_SysClk_FllDisable </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
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<p>Disables the FLL and the CCO. </p>
<dl class="section return"><dt>Returns</dt><dd><a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a> CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when function returns the PRA error status code <a class="el" href="group__group__pra__enums.html#ga60be13e12e82986f8c0d6c6a6d4f12c5">cy_en_pra_status_t</a> instead of <a class="el" href="group__group__sysclk__returns.html#gad6699a184e2e3c01433251b0981558f3">cy_en_sysclk_status_t</a>. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to <a class="el" href="group__group__pra__enums.html#ga60be13e12e82986f8c0d6c6a6d4f12c5">cy_en_pra_status_t</a> for more details.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Call <a class="el" href="group__group__startup__config__system__functions.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> after this function calling if it affects the CLK_HF0 frequency.</dd>
<dd>
Call <a class="el" href="group__group__syslib__functions.html#ga8b897f8554957f9393f645d5ab1106c9">Cy_SysLib_SetWaitStates</a> after calling this function if the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    <span class="comment">/* Scenario: FLL failed to enable and must be reconfigured. Or the FLL is no</span></div><div class="line"><span class="comment">                 longer used and hence needs to be disabled. */</span></div><div class="line"></div><div class="line">    <span class="keywordflow">if</span> (<a class="code" href="group__group__sysclk__fll__funcs.html#gab266867b8e4f71d58467c33c53f6f0e2">Cy_SysClk_FllIsEnabled</a>())</div><div class="line">    {</div><div class="line">        <span class="keywordflow">if</span> (<a class="code" href="group__group__sysclk__returns.html#ggad6699a184e2e3c01433251b0981558f3a1563f761f963757b339ff05eb5a690ec">CY_SYSCLK_SUCCESS</a> != <a class="code" href="group__group__sysclk__fll__funcs.html#ga3517689f7b87299fecbaf6eea8656146">Cy_SysClk_FllDisable</a>())</div><div class="line">        {</div><div class="line">            <span class="comment">/* Insert error handling */</span></div><div class="line">        }</div><div class="line">    }</div><div class="line"></div><div class="line">    <span class="comment">/* The clocks that relied on the FLL will now run off of the clock that</span></div><div class="line"><span class="comment">       was used to source the FLL (e.g. IMO or ECO). */</span></div></div><!-- fragment --></dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga53e22520cb9e7ee2b103d43513343803">&#9670;&nbsp;</a></span>Cy_SysClk_FllOutputDividerEnable()</h2>

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          <td class="memname">void Cy_SysClk_FllOutputDividerEnable </td>
          <td>(</td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enables/Disables the FLL output divider. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">enable</td><td></td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0e45b36747a2be6610f6fc9daefae02b">&#9670;&nbsp;</a></span>Cy_SysClk_FllGetFrequency()</h2>

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          <td class="memname">uint32_t Cy_SysClk_FllGetFrequency </td>
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          <td class="paramtype">void&#160;</td>
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<p>Returns the output frequency of the FLL. </p>
<dl class="section return"><dt>Returns</dt><dd>The output frequency of FLL.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>If the return value equals zero, that means FLL is disabled.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line">    uint32_t freq = <a class="code" href="group__group__sysclk__fll__funcs.html#ga0e45b36747a2be6610f6fc9daefae02b">Cy_SysClk_FllGetFrequency</a>();</div><div class="line">    (void) freq; <span class="comment">/* Suppress &#39;unused variable&#39; warning */</span></div></div><!-- fragment --></dd></dl>

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